This relates generally to testing integrated circuits, and more particularly, to testing integrated circuits that are packaged with test-pin-limited packages.
Integrated circuits often include test pins through which test signals are conveyed to and from the integrated circuits during device testing. The test pins are used as input-output pins during normal operation (e.g., a user mode) to convey data signals. In one conventional test arrangement, integrated circuits include test pin sharing distribution blocks (TSDB) that are used for test pin reduction purposes. The test modes used in this test arrangement include an automatic test pattern generation (ATPG) mode, a memory mode, and a phase-locked loop input-output (PLL I/O) mode.
Each test pin is used as a global test pin or a shareable test pin. A global test pin is routed to an associated circuit under test (CUT) in each test mode. A shareable test pin can be routed to as many as three associated circuits under test in each test mode (i.e., the shareable test pin is shared among the three associated CUTs). The test pin sharing distribution blocks are responsible for routing the test pins to the associated CUTs during device testing.
Scan chains such as scan chains that are compliant with the well-known Joint Test Action Group (JTAG) standard are used to load test data into associated CUTs. Scan chains (scan chain registers) are also used to capture and unload corresponding test results from CUTs. Scan chains may be accessed using one or more test pins.
The association between each test pin and the corresponding circuit(s) under test provided by the test pin sharing distribution blocks is fixed. A given test pin that is used as a shareable test pin may be associated with first, second, and third CUTs during testing (e.g., the given test pin may be connected to first, second, and third CUTs). The given test pin can be reconfigured as a global test pin that is only routed to the first CUT. In this situation, the given test pin cannot be routed to another CUT that is different from the first, second, and third CUTs in the device under test. This limited flexibility in test pin routing may make it difficult or impossible to test integrated circuits with limited test pin counts.
Another conventional test arrangement, which that is used for testing integrated circuits such as programmable integrated circuits, relies on a slow speed test mode (SSTM). Programmable integrated circuits are often organized into rows of logic array blocks (LABs). The SSTM approach involves using a single bi-directional test pin for each row of LABs. Each test pin is able to function as an input test pin during loading of test data into the device and is able to function as an output test pin during reading of test data out of the device (device verification). The SSTM approach may also have limited flexibility in test pin routing and may make it difficult to test devices with limited test pin counts.
It would therefore be desirable to be able to provide integrated circuits with improved flexibility in test pin routing.